Semiconductor processing and packaging techniques continue to evolve to meet industry demands for increased performance and reduced size. Electronic products, such as cell phones, smart phones, tablets, personal digital assistances, laptop computers, as well as other electronic devices, require packaged semiconductor assemblies having a high density of devices while having a relatively small footprint. For example, the space available for memory devices, processors, and other devices, continues to decrease in electronic products providing a need to increase the density of semiconductor devices. The thickness of semiconductor devices is continually being decreased to reduce the size of semiconductor device packages. One method to increase the density of semiconductor devices is stacking of semiconductor devices to form a semiconductor device assembly.
During the process of forming a semiconductor device assembly, the assembly may go through various processes having an elevated temperature. For example, the temperature during a reflow process to create solder joints, or interconnections, between semiconductor devices may reach an elevated temperature, such as 260 degrees Celsius. The elevated temperature may vary depending on the components of the semiconductor device assembly as well as the processes being used to form the assembly as would be appreciated by one of ordinary skill in the art.
A semiconductor device assembly may be comprised of various components such as, but not limited to, a substrate, semiconductor devices, and mold compound. Each of the components may have different coefficients of thermal expansion (CTE), which may create potential problems. As the semiconductor device assembly is subjected to an elevated temperature, the semiconductor device assembly may experience warpage due to the different CTEs of the individual components of the assembly. Warpage may provide a large amount of stress on the components of the assembly. If the warpage is too large, the warpage may create reliability issues with the interconnections within a semiconductor device assembly. For example, a warpage larger than, but not limited to, 50 microns may result in solder joint reliability issues.
Warpage may create problems in connecting a semiconductor device to a board, substrate, or to another semiconductor device. Warpage may make it very difficult to connect the two semiconductor devices. For example, warpage may cause a break in an interconnect between the two semiconductor devices if the warpage increases the distance between the two semiconductor devices. Conversely, warpage may cause a short between two adjacent interconnects if the warpage decreases the distance between the two semiconductor devices. A decrease in distance may cause the interconnect material, which may be solder, to expand laterally towards an adjacent interconnect as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. Additionally, warpage may cause components of the two semiconductor devices that are to be connected together to be misaligned.
Additional drawbacks and disadvantages may exist.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the disclosure as defined by the appended claims.